Access a vector stored in another vector in verilog

I want to access elements (8 bits long) stored in an "array", then do a logic AND with some switches. So far, not working:

module top(SW, LED);input [15:0] SW;output [15:0] LED;logic [4:0] q = {8'b11101000,8'b10011000,8'b10100010,8'b10110110,8'b10000101};assign LED[7:0] = q[0] & SW[7:0];    endmodule

I expect to have 8'b11101000 & SW[7:0] but clearly I'm not having that because of the result I'm seeing on the leds.How can I achieve this?