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Answer by dave_59 for Access a vector stored in another vector in verilog
You want const logic [4:0] q[5] = {8'b11101000, 8'b10011000, 8'b10100010, 8'b10110110, 8'b10000101};
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I want to access elements (8 bits long) stored in an "array", then do a logic AND with some switches. So far, not working: module top(SW, LED);input [15:0] SW;output [15:0] LED;logic [4:0] q =...
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